Astroparticle physics is often concerned with the observation of phenomena normally shielded by the Earth's atmosphere or taking place in the exosphere, and so demands lightweight detectors suitable for space missions hosted on satellites. In this context particle tracking is concerned with the direct measurement of the trajectory of charged particles. Currently microstrip detectors are the typical technology used in space missions, but pixel detectors, with their higher resolution and a lower material budget, represent an interesting alternative. This paper gives a brief overview of a possible design of a 3-layers particle tracker based on the ALPIDE MAPS chip. With a total of around 100 chips and the stringent constraints imposed by a space mission, the deployment and readout of such detector requires careful optimizations to limit the power consumption but at the same time maintain useful performances. Such task is approached with a custom parallel readout architecture implemented on Field Programmable Gate Arrays (FPGA), with the aim of using a single low-power FPGA chip for the entire detector.

Development of a particle tracker for space applications

Di Ruzza B.;
2020-01-01

Abstract

Astroparticle physics is often concerned with the observation of phenomena normally shielded by the Earth's atmosphere or taking place in the exosphere, and so demands lightweight detectors suitable for space missions hosted on satellites. In this context particle tracking is concerned with the direct measurement of the trajectory of charged particles. Currently microstrip detectors are the typical technology used in space missions, but pixel detectors, with their higher resolution and a lower material budget, represent an interesting alternative. This paper gives a brief overview of a possible design of a 3-layers particle tracker based on the ALPIDE MAPS chip. With a total of around 100 chips and the stringent constraints imposed by a space mission, the deployment and readout of such detector requires careful optimizations to limit the power consumption but at the same time maintain useful performances. Such task is approached with a custom parallel readout architecture implemented on Field Programmable Gate Arrays (FPGA), with the aim of using a single low-power FPGA chip for the entire detector.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11369/426694
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